Array substrate, display panel and display device

ABSTRACT

Disclosed are an array substrate, display panel and display device. The array substrate includes: a substrate, where the substrate includes a display area and a peripheral circuit area surrounding the display area; the peripheral circuit area is provided with a gate drive circuit; the gate drive circuit includes a group of shift registers connected in cascade; a first metal layer; a second metal layer; scan lines and connection structures corresponding to the scan lines one-to-one; where the first metal layer includes the scan lines; the second metal layer includes the connection structures; the shift registers include scan signal output ends; the scan signal output ends are electrically connected to the scan lines one-to-one through the connection structures; at least one end of at least one scan line is provided with an electrostatic dispersion structure; the electrostatic dispersion structure includes an electrostatic dispersion line or an first electrostatic dispersion ring.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Chinese patent application No. CN202010237445.7 filed with CNIPA on Mar. 30, 2020, the disclosure ofwhich is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, andparticularly to an array substrate, a display panel and a displaydevice.

BACKGROUND

With continuous development of science and technology, more and moreelectronic equipment with display functions are widely used in people'sdaily life and work, bringing great convenience to people's daily lifeand work, and becoming an indispensable and important tool for peopletoday.

For a display panel, which is an important component for the electronicdevice to realize the display function, an array substrate is animportant part. However, in a manufacturing process of the arraysubstrate, the substrate will have static electricity caused by thefriction between the back face of the substrate and the transfermechanism during the transfer process. The static electricity causesinduction electrification to a line on the front face of the substrate.Electrostatic discharge damage occurs when an electric field generatedby the induction electrification on the line exceeds the dielectricstrength of an insulating medium.

SUMMARY

In view of this, the present disclosure provides an array substrate, adisplay panel, and a display device.

In a first aspect, an embodiment of the present disclosure provides anarray substrate, where the array substrate includes: a display area anda peripheral circuit area surrounding the display area, where theperipheral circuit area is provided with a gate drive circuit and thegate drive circuit includes at least one group of shift registersconnected in cascade; a first metal layer, which is located on a side ofthe substrate; a second metal layer, which is located on a side of thefirst metal layer facing away from the substrate; and multiple scanlines and multiple connection structures corresponding to the multiplescan lines one-to-one.

The first metal layer includes the multiple scan lines; and the secondmetal layer includes the multiple connection structures.

The shift registers include multiple scan signal output ends; themultiple scan signal output ends are electrically connected to themultiple scan lines one-to-one through the multiple connectionstructures.

At least one end of at least one scan line of the multiple scan lines isprovided with an electrostatic dispersion structure.

The electrostatic dispersion structure includes at least oneelectrostatic dispersion line or at least one first electrostaticdispersion ring.

In a second aspect, an embodiment of the present disclosure furtherprovides a display panel, and the display panel includes the arraysubstrate of the first aspect.

In a third aspect, an embodiment of the present disclosure furtherprovides a display device. The display device includes the display panelof the second aspect.

BRIEF DESCRIPTION OF DRAWINGS

Other features, objectives and advantages of the present disclosure willbecome more apparent by reading the detailed description of thenon-limiting embodiments with reference to the following drawings:

FIG. 1 is a structure diagram illustrating a top view of a portion of anarray substrate in the related art;

FIG. 2 is a structure diagram illustrating a top view of an arraysubstrate according to an embodiment of the present disclosure;

FIG. 3 is a cross-sectional view of FIG. 2 along the Q-Q′ direction;

FIG. 4 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 5 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 6 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 7 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 8 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 9 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 10 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 11 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 12 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram illustrating a positional relationshipbetween two adjacent scan lines and a first electrostatic dispersionring according to an embodiment of the present disclosure;

FIG. 14 is a diagram illustrating a relationship between a force on acharge at point A on a first electrostatic dispersion ring and a radiusof the first electrostatic dispersion ring according to an embodiment ofthe present disclosure;

FIG. 15 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure; and

FIG. 16 is a structure diagram of a display device according to anembodiment of the present disclosure.

DETAILED DESCRIPTION

In a manufacturing process of an array substrate, a substrate, such as aglass substrate, will have static electricity caused by the frictionbetween the back face of the substrate and a transfer mechanism duringthe transfer process. The static electricity causes inductionelectrification to a line on the front face of the glass substrate.Electrostatic discharge damage occurs when an electric field generatedby the induction electrification on the line exceeds the dielectricstrength of an insulating medium. FIG. 1 is a structure diagram of aportion of an array substrate provided in the related art. As shown inFIG. 1, the array substrate in the related art includes a display areaAA′ and a peripheral circuit area AB′ surrounding the display area AA′.The display area AA′ is provided with a pixel circuit, and theperipheral circuit area AB′ is provided with a gate drive circuit. Thegate drive circuit includes one group of cascaded shift registers andmultiple signal lines. The shift register includes multiple shiftregister units 21′, and the signal lines may include a first powersupply VGH′ and a second power supply VGL′. In the related art, a firstelectrostatic discharge diode D1′ is disposed between an end of a scanline 31′ and the first power source VGH′, and a second electrostaticdischarge diode D2′ is disposed between the end of the scan line 31′ andthe second power source VGL′, so that static electricity generatedduring the manufacturing process of the array substrate is dischargedthrough the electrostatic discharge diodes. Specifically, when theinduced charges of the static electricity on the scan line 31′ ispositive and the generated voltage exceeds the first power supply VGH′,the first electrostatic discharge diode D1 is turned on to discharge apart of the positive charges exceeding the voltage range of the firstpower supply VGH′ to the second power supply VGL′, as shown by thedirection of the solid arrow in FIG. 1; when the induced charges of thestatic electricity on the scan line 31′ is negative and the generatedvoltage is lower than the second power supply VGL′, the secondelectrostatic discharge diode D2 is turned on and discharges a part ofthe negative charge exceeding the voltage range of the first powersupply VGH′ to the second power supply VGL′, as shown by the directionof the dotted arrow in FIG. 1. However, the first power supply VGH′ andthe second power supply VGL′ are located on a side of the scan line 31′facing away from the substrate. In this way, in manufacturing processesafter the formation of the scan lines 31′ and before the formation ofthe first power sources VGH′ and the second power sources VGL′, thearray substrate as a semi-finished product of the processes does nothave an anti-electrostatic function. That is, each scan lines 31′ is anisolated conductor, and the electrostatic charges induced in the scanlines 31′ cannot be discharged in the processes after the formation ofthe scan lines 31′ and before the formation of the first power sourcesVGH′ and the second power sources VGL′. Thus, when a strong electricfield generated by the charges collected at the end of the scan line 31′exceeds the dielectric strength of the insulating medium, on one hand,the strong electric field may discharge to a structure arranged on asame layer in the gate drive circuit and damage the electronic elementsin the gate drive circuit; on the other hand, the potential at eachpoint along the line in the scan line 31′ changes transiently at thebreakdown moment of the insulating medium, a transient potentialdifference occurs between an active layer (not shown) in the pixelcircuit in the display area AA′ and the scan line 31′, and when thepotential difference exceeds the antistatic capability of the insulatinglayer between the active layer and the scan line 31′, the insulatinglayer will be broken down, and a poor leakage current of the scan line31′ is generated.

Based on the above, the present disclosure provides an array substrate,a display panel, and a display device. The array substrate includes: asubstrate, where the substrate includes a display area and a peripheralcircuit area surrounding the display area, where the peripheral circuitarea is provided with a gate drive circuit and the gate drive circuitincludes at least one group of cascaded shift registers; a first metallayer, which is located on a side of the substrate; a second metallayer, which is located on a side of the first metal layer facing awayfrom the substrate; multiple scan lines and multiple connectionstructures corresponding to the scan lines in one-to-one correspondence;where the first metal layer includes the scan lines; the second metallayer includes the connection structures; the shift registers includemultiple scan signal output ends; the scan signal output ends areelectrically connected with the scan lines one-to-one through theconnection structures; at least one end of at least one scan line isprovided with an electrostatic dispersion structure; and theelectrostatic dispersion structure includes at least one electrostaticdispersion line or at least one first electrostatic dispersion ring. Inthe array substrate, the display panel and the display device providedby the present disclosure, at least one end of the scan line, that is, aplace where electrostatic charges are easily gathered, is provided withan electrostatic dispersion structure, where the electrostaticdispersion structure includes at least one electrostatic dispersion lineor at least one first electrostatic dispersion ring. Through theelectrostatic dispersion line or the first electrostatic dispersionring, the electrostatic distribution area at the end of the scan line isincreased, and the charge density of the electrostatic charge in theaccumulation area at the end of the scan line is reduced. Thereby therisk of breakdown of the insulating medium at the end of the scan lineis reduced, and the anti-electrostatic damage ability of the displaypanel in the manufacturing process is improved. In addition, the scanline is electrically connected to the shift register in the gate drivecircuit through the connection structure located in the second metallayer, that is, the static electricity at the end of the scan line isfurther discharged through the second metal layer. The damage toelectronic elements in the shift register due to the fact that staticcharges induced on the scan line are transferred to the shift registerwhen the scan line is directly and electrically connected with the shiftregister is alleviated or avoided, and the anti-electrostatic damageability of the display panel in the production process is furtherimproved.

The above is the core idea of the present disclosure. The presentdisclosure will be described clearly and completely in conjunction withthe drawings in the embodiments of the present disclosure. Based onembodiments of the present disclosure, all other embodiment obtained bythose of ordinary skill in the art on the premise of not paying creativelabor are in the scope of the protection of the present disclosure.

FIG. 2 is a structure diagram illustrating a top view of an arraysubstrate according to an embodiment of the present disclosure, and FIG.3 is a cross-sectional view of FIG. 2 taken along the Q-Q′ direction. Asshown in FIGS. 2 and 3, an array substrate provided by an embodiment ofthe present disclosure includes: a substrate 10 including a display areaAA and a peripheral circuit area AB surrounding the display area AA,where the peripheral circuit area AB is provided with a gate drivecircuit and the gate drive circuit includes at least one group ofcascaded shift registers 20; a first metal layer 30, which is located ona side of the substrate 10; a second metal layer 40, which is located ona side of the first metal layer 30 facing away from the substrate 10;multiple scan lines 31 and multiple connection structures 41 inone-to-one correspondence with the scan lines 31; where the first metallayer 30 includes the multiple scan lines 31; the second metal layer 40includes the multiple connection structures 41; the shift register 21includes multiple scan signal output ends 22; the scan signal outputends 22 are electrically connected with the scan lines 31 in aone-to-one correspondence manner through the connection structures 41;at least one end of at least one scan line 31 is provided with anelectrostatic dispersion structure 32; and the electrostatic dispersionstructure 32 includes at least one first electrostatic dispersion ring34.

Those skilled in the art may understand that, in order to facilitate thedescription of the positional relationship between the scan signaloutput end 22, the scan line 31, and the connection structure 41, FIG. 3simply shows the positional relationship of the scan signal output end22, the scan line 31, and the connection structure 41. However, inpractice, the array substrate also includes other signal lines anddevices, which are not shown here.

Specifically, by providing at least one first electrostatic dispersionring 34 at at least one end of at least one scan line 31, that is, aplace where electrostatic charges are easily gathered, the electrostaticdistribution area at the end of the scan line 31 is increased throughthe first electrostatic dispersion ring 34, the charge density of acharge accumulation area at the end of the scan line 31 is reduced, therisk that an insulating medium at the end of the scan line 31 is brokendown is further reduced, and the antistatic damage ability of thedisplay panel in the manufacturing process is improved. In addition, thescan line 31 is electrically connected to the shift register 20 in thegate drive circuit through the connection structure located in thesecond metal layer 40, that is, the static electricity at the end of thescan line 31 is further discharged through the second metal layer 40.The damage to electronic elements in the shift register 20 due to thefact that electrostatic charges induced on the scan line 31 aretransferred to the shift register 20 when the scan line 31 is directlyand electrically connected with the shift register 20 is alleviated oravoided, and the anti-electrostatic damage ability of the display panelin the production process is further improved.

It should be noted that the electrostatic dispersion structure 32 may beprovided at only one end of the scan line 31, or the electrostaticdispersion structure 32 may be provided at both ends of the scan line 31respectively; and the electrostatic dispersion structure may be providedat at least one end of one scan line 31, or may also be provided at atleast one end of each and every scan line 31, which are not specificallylimited in the embodiment, and may be chosen by those skilled in the artaccording to actual conditions. FIG. 2 is only an exemplary illustrationin which the electrostatic dispersion ring 34 is provided at one end ofeach scan line 31.

FIG. 4 is a structure diagram illustrating a top view of another arraysubstrate according to an embodiment of the present disclosure. As shownin FIG. 4, the array substrate provided by the embodiment of the presentdisclosure includes: a substrate 10 including a display area AA and aperipheral circuit area AB surrounding of the area AA, where theperipheral circuit area AB is provided with a gate drive circuit and thegate drive circuit includes at least one group of cascaded shiftregisters 20; a first metal layer 30, which is located on a side of thesubstrate 10; a second metal layers 40, which is located on a side ofthe first metal layer 30 facing away from the substrate 10; multiplescan lines 31 and multiple connection structures 41 corresponding to thescan lines 31 one-to-one; where the first metal layer 30 includes themultiple scan lines 31; the second metal layer 40 includes the multipleconnection structures 41; the shift register 21 includes multiple scansignal output ends 22; the multiple scan signal output ends 22 areelectrically connected to the multiple scan lines 31 through themultiple connection structures 41 in one-to-one correspondence; at leastone end of at least one scan line 31 is provided with an electrostaticdispersion structure 32; and the electrostatic dispersion structure 32includes at least one electrostatic dispersion line 33.

Specifically, by providing at least one electrostatic dispersion line 33at at least one end of at least one scan line 31, that is, a place whereelectrostatic charges are easily gathered, the electrostaticdistribution area at the end of the scan line 31 is increased throughthe electrostatic dispersion line 33, the charge density of a chargeaccumulation area at the end of the scan line 31 is reduced, the riskthat an insulating medium at the end of the scan line 31 is broken downis further reduced, and the antistatic damage ability of the displaypanel in the manufacturing process is improved. In addition, the scanline 31 is electrically connected to the shift register 20 in the gatedrive circuit through the connection structure located in the secondmetal layer 40, that is, the static electricity at the end of the scanline 31 is further discharged through the second metal layer 40. Thedamage to electronic elements in the shift register due to the fact thatelectrostatic charges induced on the scan line are transferred to theshift register when the scan line 31 is directly and electricallyconnected with the shift register is alleviated or avoided, and theanti-electrostatic damage ability of the display panel in the productionprocess is further improved.

In one or more embodiments, the substrate 10 has functions of supportingand protecting other film layers in the array substrate, and film layersof the array substrate are formed on the substrate 10. The substrate 10may be a rigid substrate or a flexible substrate, where a material ofthe rigid substrate may be glass, a material of the flexible substratemay be polyimide, and a thickness of the substrate 10 may be setaccording to process requirements and product requirements. In one ormore embodiments, the array substrate may include pixel circuitsarranged in an array, where pixel circuits in one row are electricallyconnected to one scan line 31, one pixel circuit includes at least onethin film transistor, and the thin film transistor includes an activelayer, a gate electrode, a source electrode and a drain electrode. Thearray substrate also includes a semiconductor layer on a side of thesubstrate 10, an insulating layer between the semiconductor layer andthe first metal layer, and an insulating layer between the first metallayer and the second metal layer, etc., where the semiconductor layerincludes an active layer, the first metal layer includes the scan lineand the gate electrode, the second metal layer includes a connectionstructure, the source electrode and the drain electrode, and thematerial of the insulating layer may include silicon oxide or siliconnitride, which is not limited by the embodiment of the presentdisclosure. When the second metal layer includes the connectionstructure, the source electrode and the drain electrode, the connectionstructure, the source electrode and the drain electrode are formed ofthe same material in the same process, that is, the connection structureis formed at the same time with the source electrode and the drainelectrode. No additional process is needed, so that the process flow issimplified, and the manufacturing cost of the display panel is reduced.

In one or more embodiments, referring to FIG. 2, the gate drive circuitincludes a group of cascaded shift registers 20 located on one side ofthe display area AA. During a display process, the shift registers 20output scan signals to the corresponding scan lines 31 through the scansignal output end 22, the cascaded shift registers 20 sequentiallyoutput the scan signals to the scan lines 31, the pixel units in thedisplay panel receive the corresponding scan signals line by line andare turned on correspondingly, the signals on the data signal lines areinput to the corresponding pixel units, and the display panel achieves adisplay function.

In one or more embodiments, FIG. 5 is a structure diagram illustrating atop view of another array substrate according to an embodiment of thepresent disclosure. Referring to FIG. 5, the gate drive circuit includestwo groups of cascaded shift registers 20 on opposite sides of thedisplay area AA. When the gate drive circuit includes two groups ofcascaded shift registers 20 on opposite sides of the display area AA,during the display process, the shift register units in the two groupsof shift registers 20 disposed on different sides are electricallyconnected through scan lines 31, and the shift register units in theshift registers 20 electrically connected to the same scan line 31synchronously output scan signals to the scan line 31, so as to avoidthe influence of a voltage drop on the scan line 31 on the displayeffect of the display panel.

It should be noted that the size ratio of the display area AA and theperipheral circuit area AB in the drawings, and the size of structuresin the drawings are only illustrative. The size ratio and the size maybe set according to actual needs.

In summary, in the array substrate provided by the embodiment of thepresent disclosure, at least one end of the scan line, that is, a placewhere electrostatic charges are easily gathered, is provided with anelectrostatic dispersion structure, where the electrostatic dispersionstructure includes at least one electrostatic dispersion line or atleast one first electrostatic dispersion ring. Through the electrostaticdispersion line or the first electrostatic dispersion ring, theelectrostatic distribution area at the end of the scan line is increasedand the charge density of the electrostatic charges in the accumulationarea at the end of the scan line is reduced. Thereby the risk ofbreakdown of the insulating medium at the end of the scan line isreduced, and the anti-electrostatic damage ability of the display panelin the manufacturing process is improved. In addition, the scan line iselectrically connected to the shift register in the gate drive circuitthrough the connection structure located in the second metal layer, thatis, the static electricity at the end of the scan line is furtherdischarged through the second metal layer. The damage to electronicelements in the shift register due to the fact that static chargesinduced on the scan line are transferred to the shift register when thescan line is directly and electrically connected with the shift registeris alleviated or avoided, and the anti-electrostatic damage ability ofthe display panel in the production process is further improved.

On the basis of the above, in one or more embodiments, with continuedreference to FIG. 2, along an extending direction of the scan line 31,an area where the electrostatic dispersion structure 32 is located has asize of L2, where 0<L2≤L1, where L1 is an interval between two adjacentscan lines.

In one or more embodiments, in order to increase an area of theelectrostatic distribution, the size L2 of the area where theelectrostatic dispersion structure 32 is located may be adjusted freelyin an extending direction of the scan line 31, which is not specificallylimited in the embodiment. For example, the size of the area where theelectrostatic discharge structure 32 is located may be larger than theinterval L1 between two adjacent scan lines 31.

In one or more embodiments, the size L2 of the area where theelectrostatic discharge structure 32 is located may be smaller than orequal to the interval L1 between two adjacent scan lines 31.Specifically, when the electrostatic dispersion structure 32 is thefirst electrostatic dispersion ring 34, a width of the firstelectrostatic dispersion ring 34 should not be too large in a directionperpendicular to the scan line 31 due to the influence of the intervalbetween the adjacent scan lines 31. Therefore, when the electrostaticdispersion structure 32 is the first electrostatic dispersion ring 34,the width of the first electrostatic dispersion ring 34 in the extendingdirection of the scan line 31 may be the same as the size in a directionperpendicular to the scan line 31, and the size of the area where thefirst electrostatic dispersion ring 34 is located is at most equal tothe interval L1 between two adjacent scan lines 31 in the directionperpendicular to the scan line 31. In the embodiment, along theextending direction of the scan line 31, the size of the area where thefirst electrostatic dispersion ring 34 is located is L2, and 0<L2≤L1,where L1 is an interval between two adjacent scan lines 31. In this way,the electrostatic distribution area may be increased, and it is alsopossible to avoid the risk that the width of the electrostaticdispersion ring 32 in the extending direction of the scan line 31becomes long, in which case the curvature of the electrostaticdispersion ring 32 becomes too large, and electrostatic charges areeasily accumulated at corners of the electrostatic dispersion ring 32,causing breakdown of the dielectric at the corners.

Referring to FIG. 4, when the electrostatic dispersion structure 32 isthe electrostatic dispersion line 33, because of the repulsive forcebetween the charges of a same polarity, the electrostatic charges aredistributed at the ends of the electrostatic dispersion line 33.Therefore, the projection of the area of the electrostatic distributionon the substrate 10 corresponds to the distribution being on the sameclosed pattern, and the closed pattern may be, for example, a regularpattern or an irregular pattern, and the regular pattern may include,for example, a circular ring or an elliptical ring, that is, a patterncorresponding to the electrostatic dispersion ring. When theelectrostatic dispersion structure 32 is the electrostatic dispersionline 33, the width of the electrostatic dispersion line 33 in theextending direction of the scan line 31 should be the same as the sizein the direction perpendicular to the scan line 31, while the size ofthe area where the electrostatic dispersion line 33 is located is atmost equal to the interval L1 between two adjacent scan lines 31 in thedirection perpendicular to the scan line 31. Therefore in theembodiment, along the extending direction of the scan line 31, the areawhere the electrostatic dispersion line is located has a size of L2,where 0<L2≤L1, where the interval between two adjacent scan lines 31 isL1. Thus, the area of the electrostatic distribution may be increased,and the electrostatic charges can be prevented from being accumulatedand breaking down the dielectric due to the increase in curvature of thearea surrounded by the end portion of the electrostatic dispersion line33.

In one or more embodiments, FIG. 6 is a structure diagram illustrating atop view of another array substrate according to an embodiment of thepresent disclosure. As shown in FIG. 6, two ends of the scan line 31 arerespectively provided with electrostatic dispersion structures 32; in adirection perpendicular to the scan line 31, the electrostaticdispersion structures 32 at both ends of the scan line 31 aresymmetrical about the center line OO of the display area AA.

In the embodiment, by disposing electrostatic dispersion structures 32at two ends of the scan line 31, the electrostatic charges induced onthe scan line 31 are dispersed by the electrostatic dispersionstructures at the two ends of the scan line 31, thereby the chargedensity of the charge accumulation area at the ends of the scan linedensity is reduced. Further, the electrostatic dispersion structure 32is symmetrical about the center line OO of the display area AA, so thatthe induced electrostatic charges are evenly distributed on both ends ofthe scan line 31 along the extending direction of the scan line 31, andthe charge density of the charge accumulation area at the ends of thescan line is further reduced. Thereby the risk of breakdown of theinsulating medium at the ends of the scan line is reduced, and theanti-electrostatic damage ability of the display panel during themanufacturing process is improved.

The following is a detailed description of a typical example when theelectrostatic dispersion structure includes at least one electrostaticdispersion line. It should be understood that none of the followingcontents is intended to limit the present disclosure.

In one or more embodiments, FIG. 7 is a structure diagram illustrating atop view of another array substrate according to an embodiment of thepresent disclosure. As shown in FIG. 7, the electrostatic dispersionstructure 32 includes at least one electrostatic dispersion line 33, andthe shape of the vertical projection of the electrostatic dispersionline 33 on the plane where the substrate 10 is located includes a lineshape. FIG. 8 is a structure diagram of another array substrateaccording to an embodiment of the present disclosure. As shown in FIG.8, the electrostatic dispersion structure 32 includes at least oneelectrostatic dispersion line 33, and the shape of the verticalprojection of the electrostatic dispersion line 33 on the plane wherethe substrate 10 is located includes a wavy shape. FIG. 9 is a structurediagram of another array substrate according to an embodiment of thepresent disclosure. As shown in FIG. 9, the electrostatic dispersionstructure 32 includes at least one electrostatic dispersion line 33, andthe shape of the vertical projection of the electrostatic dispersionline 33 on the plane where the substrate 10 is located includes a zigzagshape.

In the embodiment, when the shape of the vertical projection of theelectrostatic dispersion line 33 on the plane where the substrate 10 islocated includes a line shape, a wavy shape or a zigzag shape, theelectrostatic dispersion structure 33 of the line shape, the wavy shapeor zigzag shape disperses the electrostatic charge induced on the scanline 31, and the charge density of the charge accumulation area at theends of the scan line 31 is reduced. Thereby the risk of breakdown ofthe insulating medium at the ends of the scan line 31 is reduced, andthe anti-electrostatic damage ability of the display panel during themanufacturing process is improved.

Those skilled in the art may understand that the shape of the verticalprojection of the electrostatic dispersion line 33 on the plane of thesubstrate 10 includes, but is not limited to, the above examples. Thoseskilled in the art may set the shape of the electrostatic dispersionline 33 according to the product requirements. There is no specificlimitation in the disclosure.

It should be noted that FIGS. 7, 8, and 9 exemplify that theelectrostatic dispersion lines 33 are disposed at two ends of the scanlines 31, and the electrostatic dispersion lines 33 are disposed at theends of each scan line 31. The specific arrangements shown is notintended to limit the present application.

In one or more embodiments, with continued reference to FIG. 4, theelectrostatic dispersion structure 32 includes at least oneelectrostatic dispersion line 33. The line width of the electrostaticdispersion line 33 is M1, where 0<M1≤2×L3, where the line width of thescan line 31 is L3.

In the embodiment, the line width of the electrostatic dispersion line33 is set to be less than or equal to twice the line width L3 of thescan line 31, so that the load of the electrostatic dispersion line 33will not increase because the width of the electrostatic dispersion line33 is too large, that is, the electrostatic charges at the end of thescan line 31 can be dispersed without adding additional load.

In one or more embodiments, with continued reference to FIG. 4, theelectrostatic dispersion structure 32 includes multiple electrostaticdispersion lines 33. An interval between adjacent electrostaticdispersion lines is L4, where L2/10<L4≤L2, where L2 is a size of an areawhere the electrostatic dispersion structure is located.

In the embodiment, the interval between adjacent electrostaticdispersion lines 33 is L4, and L2/10<L4≤L2. In this way, the number ofelectrostatic dispersion lines 33 is not reduced since the intervalbetween adjacent electrostatic dispersion lines 33 is too large. On onehand, if the number of electrostatic dispersion lines 33 is reduced, theelectrostatic charges divided to each electrostatic dispersion line 33will increase under the same total amount of electrostatic charge, theelectric field intensity at the end of the electrostatic dispersion line33 will become larger, and the risk of breakdown of the medium isincreased. At the same time, the number of electrostatic dispersionlines 33 is not increased since the interval between adjacentelectrostatic dispersion lines 33 is too small, since if the number ofelectrostatic dispersion lines 33 becomes larger, the load will alsobecome larger. Therefore, based on this, through theoretical calculation(Huygens principle), when the interval between adjacent electrostaticdispersion lines 33 is less than 11% of one half of the size of the areawhere the electrostatic dispersion structure 32 is located, theelectrostatic dispersion effect is 95%, and the load will not beincreased. Therefore, in the embodiment, the interval between adjacentelectrostatic dispersion lines 33 may be L4, where L2/10<L4≤L2, wherethe area where the electrostatic dispersion structure 32 is located hasa size of L2, so that the electrostatic dispersion effect is ensured andthe load of the electrostatic dispersion structure 32 is not increased.

It should be noted that FIG. 4 only exemplarily shows that theelectrostatic dispersion structure 32 includes three electrostaticdispersion lines 33, and is not intended to limit the application. Thoseskilled in the art may set the number of electrostatic dispersion linesaccording to the product requirements, for example, by setting thenumber of the electrostatic dispersion lines 33 to 10. Hereinafter, alsofor explaining the positional relationship of the electrostaticdispersion lines 33, the number of the electrostatic dispersion lines 33is exemplarily shown, and those skilled in the art may actually set thenumber of the electrostatic dispersion lines 33 according to the productrequirements, which is not shown here.

In one or more embodiments, FIG. 10 is a structure diagram illustratinga top view of another array substrate according to an embodiment of thepresent disclosure. As shown in FIG. 10, the electrostatic dispersionstructure 32 includes multiple electrostatic dispersion lines 33, andthe vertical distances from the ends of the multiple electrostaticdispersion lines 33 to the scan line 31 are different in the directionperpendicular to the scan lines 31.

In the embodiment, the vertical distances from the ends of the multipleelectrostatic dispersion lines 33 to the scan lines 31 are differentalong the direction perpendicular to the scan lines 31, so that thedistance between the static electricity charges at the ends of theadjacent electrostatic dispersion lines 31 is reduced, the repulsiveforce between the static electricity charges at the ends of the adjacentelectrostatic dispersion lines 31 is further reduced, and the risk thatthe static electricity charges distributed on the electrostaticdispersion lines 31 move to the scan lines 31 under the repulsive forceand break down the medium is avoided.

In one or more embodiments, with continued reference to FIG. 7, theelectrostatic dispersion structure 32 includes multiple electrostaticdispersion lines 33, and the vertical distances from the ends of themultiple electrostatic dispersion lines 33 to the scan line 31 aredifferent in the direction perpendicular to the scan lines 31.

In the embodiment, when the vertical distances from the ends of themultiple electrostatic dispersion lines 33 to the scan line 31 are thesame, the same process may be adopted when forming the multipleelectrostatic dispersion lines 33, the process steps are simplified, andthe production efficiency is improved.

In one or more embodiments, FIG. 11 is a structure diagram illustratinga top view of another array substrate according to an embodiment of thepresent disclosure. As shown in FIG. 11, the extending direction of themultiple electrostatic dispersion lines 31 are perpendicular to the scanline 31, and the vertical projections of the ends of the multipleelectrostatic dispersion lines 31 on the substrate 10 are distributed ona same circle.

Since a repulsive force exists between electrostatic charges of the samepolarity and the magnitude of the repulsive force is inverselyproportional to the distance between the electrostatic charges, theelectrostatic charge density at each point on an irregular conductor isproportional to the curvature at that point. When the verticalprojections of the ends of the multiple electrostatic dispersion lines33 on the substrate 10 are distributed on the same circle, thedispersion effect of the electrostatic charge is uniform, and the riskof breakdown of the medium due to the accumulation of electrostaticcharges on the scan line 31 is avoided.

In one or more embodiments, with continued reference to FIG. 11, theintervals between adjacent electrostatic dispersion lines 33 are equal.

In the embodiment, when the intervals between adjacent electrostaticdispersion lines 33 are equal, the electrostatic charges are furtheruniformly distributed on the electrostatic dispersion lines 33. In thisway, the risk of breakdown of the medium due to the accumulation ofelectrostatic charges on the scan line 31 is further avoided.

In one or more embodiments, FIG. 12 is a structure diagram illustratinga top view of another array substrate according to an embodiment of thepresent disclosure. As shown in FIG. 12, the electrostatic dispersionstructure 32 includes at least one electrostatic dispersion line 33, andthe electrostatic dispersion structure 32 further includes a secondelectrostatic dispersion ring 36 disposed at an end of the electrostaticdispersion line 33.

When the electrostatic dispersion line 33 is provided at an end of thescan line 31, the static electricity induced on the scan line 31 will bedispersed at the end of the electrostatic dispersion line 33. Therefore,if the amount of charge of the induced static electricity is too large,there is still a risk of breakdown of the insulating medium at the end.Therefore, in the embodiment, by providing the second electrostaticdispersion ring 36 at the end of the electrostatic dispersion line 33,that is, the area where static charges accumulate, the electrostaticdistribution area of the end of the electrostatic dispersion line 33 isfurther expanded and the charge density of the charge accumulation areaat the end of the electrostatic dispersion line 33 is reduced. Therebythe risk of breakdown of the insulating medium at the end of theelectrostatic dispersion line 33 is reduced, and the anti-electrostaticdamage ability of the display panel during the manufacturing process isfurther improved.

In one or more embodiments, with continued reference to FIG. 12, acorner of the second electrostatic dispersion ring 36 is arc-shaped.

Since the charge density is proportional to the curvature, if thecurvature at the corner of the second electrostatic dispersion ring 36is large, the electrostatic charge may accumulate at the corner,resulting in the risk of breakdown of the medium at the corner.Therefore, in the embodiment, by setting the corner of the secondelectrostatic dispersion ring 36 to be arc-shaped, the risk of breakdownof the medium at the corner due to electrostatic charge accumulating ata sharp corner in a case of the sharp corner of the second electrostaticdispersion ring 36 is avoided.

The above is a detailed description of a typical example when theelectrostatic dispersion structure includes at least one electrostaticdispersion line.

The following is a detailed description with a typical example when theelectrostatic dispersion structure includes at least one electrostaticdispersion ring. None of the following contents is intended to limit thepresent disclosure.

In one or more embodiments, with continued reference to FIG. 2, theelectrostatic dispersion structure 32 further includes at least onefirst electrostatic dispersion ring 34, and a corner of the firstelectrostatic dispersion ring 34 is arc-shaped.

If the curvature at the corner of the first electrostatic dispersionring 34 is large, electrostatic charges may accumulate at the corner,resulting in the risk of breakdown of the medium at the corner.Therefore, in the embodiment, by setting the corner of the firstelectrostatic dispersion ring 34 to be arc-shaped, the risk of breakdownof the medium at the corner due to electrostatic charge accumulating atthe sharp corner in a case of the sharp corner of the firstelectrostatic dispersion ring 34 is avoided.

In one or more embodiments, with continued reference to FIG. 2, thevertical projection of the first electrostatic dispersion ring 34 on thesubstrate 10 has a shape of a circular ring; and the radius of thecircular ring is R, where 0<R<(½)×L1, where the interval between twoadjacent scan lines 31 is L1.

FIG. 13 is a schematic diagram illustrating a position relationshipbetween two adjacent scan lines and a first electrostatic dispersionring according to an embodiment of the present disclosure, and FIG. 14is a diagram illustrating a relationship between force on a charge atpoint A on a first electrostatic dispersion ring and a radius of thefirst electrostatic dispersion ring according to an embodiment of thepresent disclosure. The abscissa represents the radius R of the firstelectrostatic dispersion ring, and the ordinate represents the repulsiveforce of the electric charge on point A and the electric charges on aportion, which is close to the point A and has a radian of 2θ, of afirst electrostatic dispersion ring provided at the end of the adjacentscan line. Specifically, the radius of the circular ring is R, theinterval between two adjacent scan lines 31 is L1, and the electricforce applied by the adjacent first electrostatic dispersion ring on theelectric charge at point A is generated by the electric charges on aportion having a radian of 2θ of the first electrostatic dispersionring. Since the force between point charges is F=k×(q1×q2)/(r²), whenthe distance of the first electrostatic dispersion rings 34 at the endsof the adjacent scan lines 31 is large enough, the charge density oneach first electrostatic dispersion ring is Q/(2πR), andcos(θ)=R/(L1−R). The point A and an area around the point A, for examplethe length of this area being L, will be subject to the repulsive forceof the electric charges on the portion close to the point A and having aradian of 2θ of the first electrostatic dispersion ring provided at theend of the adjacent scan line, and the force applied on the charges atthe point A and the area around the point A is F, whereF≈k×((Q/2πR)×L)×(Q/2πR)×2θ/(L1−2R)². Based on this, the applicantmeasured the relationship between the charge force at the point A andthe area around point A and the radius of the semi-circle. Referring toFIG. 14, as the radius R of the circular ring increases, the forceapplied on the charge at the point A decreases. Thus, it is concludedthat when the radius of the circular ring is at the maximum, that is,half of the interval between the two adjacent scan lines, the force atthe point A is at the minimum. Therefore, in the embodiment, by settingthe radius of the circular ring to be greater than zero and less thanhalf of the interval L1 between two adjacent scan lines 31, theelectrostatic charge may be dispersed, the repulsive force of theelectrostatic charges on adjacent first electrostatic dispersion ringsis at the minimum, the electrostatic charge can be evenly and stablydistributed on the first electrostatic dispersion ring 34, and the riskthat the electrostatic charges distributed on the first electrostaticdispersion ring 34 may move to the scan line 31 under the repulsiveforce and cause breakdown of the medium is avoided.

In one or more embodiments, with continued reference to FIG. 2, the linewidth of the first electrostatic dispersion ring 34 is M2, where0<M2≤2×L3, where L3 is the line width of the scan line 31.

In the embodiment, the line width of the first electrostatic dispersionring 34 is set to be greater than 0 and less than or equal to twice theline width L3 of the scan line 31, so that the load of the electrostaticdispersion ring 34 will not increase because the width of theelectrostatic dispersion ring 34 is too large, that is, in theembodiment, the line width of the first electrostatic dispersion ring 34is M2, where 0<M2≤2×L3, where the line width of the scan line 31 is L3,and the electrostatic charges at the end of the scan line 31 can bedispersed without adding additional load.

In one or more embodiments, with continued reference to FIG. 2, theelectrostatic dispersion structure 32 includes one first electrostaticdispersion ring 34, and the first electrostatic dispersion ring 34 isaxially symmetrical about the scan line 31.

In the embodiment, the first electrostatic dispersion ring 34 is axiallysymmetrical about the scan line 31, so that the induced electrostaticcharges are evenly distributed on both sides of the scan line 31 in adirection perpendicular to the scan line 31, and the risk of breakdownof the medium due to a large local electric field at the end of the scanline 31 is avoided.

In one or more embodiments, FIG. 15 is a structure diagram illustratinga top view of another array substrate according to an embodiment of thepresent disclosure. As shown in FIG. 10, the electrostatic dispersionstructure 32 includes two first electrostatic dispersion rings 34, andthe two first electrostatic dispersion rings 34 are axially symmetricalabout the scan line 31.

When the electrostatic dispersion structure 32 includes the two firstelectrostatic dispersion rings 34, while not increasing the load, thearea of electrostatic charge dispersion is increased, and the chargedensity of the charge accumulation area at the end of the scan line isreduced. Thereby the risk of breakdown of the insulating medium at theend of the scan line is reduced, and the anti-electrostatic damageability of the display panel in the manufacturing process is improved.Further, the two first electrostatic dispersion rings 34 are axiallysymmetrical about the scan line 31, so that the electrostatic charge atthe end of the scan line is evenly distributed on both sides of the scanline to avoid the risk of breakdown of the medium due to the large localelectric field when the electrostatic charge is accumulated on one side.

It should be noted that FIG. 15 only exemplarily shows that theelectrostatic dispersion structure 32 includes two first electrostaticdispersion rings 34, and the two first electrostatic dispersion rings 34are axially symmetrical about the scan line 31. This example is notintended to limit the application. Those skilled in the art may set thenumber of electrostatic dispersion lines according to the productrequirements, for example, the electrostatic dispersion structure 32including four first electrostatic dispersion rings 34 and the fourfirst electrostatic dispersion rings 34 being axially symmetrical aboutthe scan line 31; or the electrostatic dispersion structure 32 includingsix first electrostatic dispersion rings 34 and the six firstelectrostatic dispersion rings 34 being axially symmetrical about thescan line 31.

Based on the same inventive concept, an embodiment of the presentdisclosure also provides a display panel, including the array substrateof any embodiment of the present disclosure. Since the display panelprovided by the embodiment of the present disclosure includes any one ofthe array substrates provided by the above embodiments, the displaypanel has the same or corresponding technical effects as the arraysubstrate provided by the above embodiments.

In one or more embodiments, the display panel provided by the embodimentof the present disclosure may be an organic light-emitting diode displaypanel or a liquid crystal display panel.

Based on the same inventive concept, an embodiment of the presentdisclosure also provides a display device, including the array substrateof any embodiment of the present disclosure. Specifically, FIG. 16 is astructure diagram of a display device provided by an embodiment of thepresent disclosure. As shown in FIG. 16, the display device 100 includesthe display panel 101 provided by the above embodiment. Exemplarily, thedisplay device 100 may be an electronic device such as a mobile phone, acomputer, a smart wearable device (for example, a smart watch), or avehicle-mounted display device, which is not limited in the presentdisclosure.

What is claimed is:
 1. An array substrate, comprising: a substrate,wherein the substrate comprises a display area and a peripheral circuitarea surrounding the display area; the peripheral circuit area isprovided with a gate drive circuit; and the gate drive circuit comprisesat least one group of shift registers connected in cascade; a firstmetal layer, which is located on a side of the substrate; a second metallayer, which is located on a side of the first metal layer facing awayfrom the substrate; and a plurality of scan lines and a plurality ofconnection structures corresponding to the plurality of scan linesone-to-one; wherein the first metal layer comprises the plurality ofscan lines; the second metal layer comprises the plurality of connectionstructures; the shift registers comprise a plurality of scan signaloutput ends; the plurality of scan signal output ends are electricallyconnected to the plurality of scan lines one-to-one through theplurality of connection structures; at least one end of at least onescan line of the plurality of scan lines is provided with anelectrostatic dispersion structure; and the electrostatic dispersionstructure comprises one of: at least one electrostatic dispersion line,or at least one first electrostatic dispersion ring.
 2. The arraysubstrate of claim 1, wherein along an extending direction of the atleast one scan line, an area where the electrostatic dispersionstructure is located has a size of L2, wherein 0<L2≤L1, wherein L1 is aninterval between each two adjacent scan lines of the plurality of scanlines.
 3. The array substrate of claim 1, wherein the at least one scanline is provided with electrostatic dispersion structures at both endsof the at least one scan line; and the electrostatic dispersionstructures at both ends of at least one scan line are symmetrical abouta center line of the display area; and the center line is parallel to adirection perpendicular to the at least one scan line.
 4. The arraysubstrate of claim 1, wherein the electrostatic dispersion structurecomprises at least one electrostatic dispersion line; and a verticalprojection of the electrostatic dispersion line on a plane where thesubstrate is located has one of a line shape, a wavy shape or a zigzagshape.
 5. The array substrate of claim 1, wherein the electrostaticdispersion structure comprises at least one electrostatic dispersionline; the electrostatic dispersion line has a line width of M1, wherein0<M1≤2×L3, wherein L3 is a line width of each of the plurality of scanlines.
 6. The array substrate of claim 2, wherein the electrostaticdispersion structure comprises a plurality of electrostatic dispersionlines; an interval between each adjacent electrostatic dispersion linesof the plurality of electrostatic dispersion lines is L4, andL2/10<L4≤L2, wherein L2 is a size of an area where the electrostaticdispersion structure is located.
 7. The array substrate of claim 1,wherein the electrostatic dispersion structure comprises a plurality ofelectrostatic dispersion lines; in a direction perpendicular to the scanline, vertical distances from ends of the plurality of electrostaticdispersion lines to the at least one scan line are different.
 8. Thearray substrate of claim 7, wherein the extending direction of theplurality of electrostatic dispersion lines is perpendicular to the atleast one scan line, and vertical projections of the ends of theplurality of electrostatic dispersion lines on the substrate arearranged on a same circle.
 9. The array substrate of claim 8, whereineach adjacent electrostatic dispersion line of the plurality ofelectrostatic dispersion lines has an equal interval.
 10. The arraysubstrate of claim 1, wherein the electrostatic dispersion structurecomprises at least one electrostatic dispersion line; and theelectrostatic dispersion structure further comprises a secondelectrostatic dispersion ring disposed at an end of the electrostaticdispersion line.
 11. The array substrate of claim 10, wherein a cornerof the second electrostatic dispersion ring is arc-shaped.
 12. The arraysubstrate of claim 1, wherein the electrostatic dispersion structurecomprises at least one first electrostatic dispersion ring; and a cornerof the first electrostatic dispersion ring is arc-shaped.
 13. The arraysubstrate of claim 12, wherein a vertical projection of the firstelectrostatic dispersion ring on the substrate has a shape of a circularring; and the circular ring has a radius of R, wherein 0<R<(½)×L1,wherein L1 is an interval between each two adjacent scan lines of theplurality of scan lines.
 14. The array substrate of claim 12, whereinthe first electrostatic dispersion ring has a line width of M2, wherein0<M2≤2×L3, wherein L3 is a line width of each of the plurality of scanlines.
 15. The array substrate of claim 12, wherein the electrostaticdispersion structure comprises one first electrostatic dispersion ring;and the first electrostatic dispersion ring is axially symmetrical aboutthe at least one scan line.
 16. The array substrate of claim 1, whereinthe electrostatic dispersion structure comprises two first electrostaticdispersion rings; and the two first electrostatic dispersion rings aredisposed axially symmetrically about the at least one scan line.
 17. Adisplay panel, comprising an array substrate, wherein the arraysubstrate comprises: a substrate, wherein the substrate comprises adisplay area and a peripheral circuit area surrounding the display area;the peripheral circuit area is provided with a gate drive circuit; andthe gate drive circuit comprises at least one group of shift registersconnected in cascade; a first metal layer, which is located on a side ofthe substrate; a second metal layer, which is located on a side of thefirst metal layer facing away from the substrate; and a plurality ofscan lines and a plurality of connection structures corresponding to theplurality of scan lines one-to-one; wherein the first metal layercomprises the plurality of scan lines; the second metal layer comprisesthe plurality of connection structures; the shift registers comprise aplurality of scan signal output ends; the plurality of scan signaloutput ends are electrically connected to the plurality of scan linesone-to-one through the plurality of connection structures; at least oneend of at least one scan line of the plurality of scan lines is providedwith an electrostatic dispersion structure; and the electrostaticdispersion structure comprises one of: at least one electrostaticdispersion line, or at least one first electrostatic dispersion ring.18. A display device, comprising a display panel, wherein the displaypanel comprises an array substrate, and the array substrate comprises: asubstrate, wherein the substrate comprises a display area and aperipheral circuit area surrounding the display area; the peripheralcircuit area is provided with a gate drive circuit; and the gate drivecircuit comprises at least one group of shift registers connected incascade; a first metal layer, which is located on a side of thesubstrate; a second metal layer, which is located on a side of the firstmetal layer facing away from the substrate; and a plurality of scanlines and a plurality of connection structures corresponding to theplurality of scan lines one-to-one; wherein the first metal layercomprises the plurality of scan lines; the second metal layer comprisesthe plurality of connection structures; the shift registers comprise aplurality of scan signal output ends; the plurality of scan signaloutput ends are electrically connected to the plurality of scan linesone-to-one through the plurality of connection structures; at least oneend of at least one scan line of the plurality of scan lines is providedwith an electrostatic dispersion structure; and the electrostaticdispersion structure comprises one of: at least one electrostaticdispersion line, or at least one first electrostatic dispersion ring.